`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/11/23 22:57:01
// Design Name: 
// Module Name: eqcmp
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

`include "funct.vh"
module lord_t(
	input wire [1:0] offset,
	input wire [2:0] lordM,
	input wire [31:0] memdata,
	output wire [31:0] newReaddataM,
	output wire addrload
    );
	assign newReaddataM = (lordM==`Sign_LB && offset==2'b00)?{{24{memdata[7]}},memdata[7:0]}:
	(lordM==`Sign_LB && offset==2'b01)?{{24{memdata[15]}},memdata[15:8]}:
	(lordM==`Sign_LB && offset==2'b10)?{{24{memdata[23]}},memdata[23:16]}:
	(lordM==`Sign_LB && offset==2'b11)?{{24{memdata[31]}},memdata[31:24]}:
	(lordM==`Sign_LBU && offset==2'b00)?{{24{0}},memdata[7:0]}:
	(lordM==`Sign_LBU && offset==2'b01)?{{24{0}},memdata[15:8]}:
	(lordM==`Sign_LBU && offset==2'b10)?{{24{0}},memdata[23:16]}:
	(lordM==`Sign_LBU && offset==2'b11)?{{24{0}},memdata[31:24]}:
	(lordM==`Sign_LH && offset[1]==1'b0)?{{16{memdata[15]}},memdata[15:0]}:
	(lordM==`Sign_LH && offset[1]==1'b1)?{{16{memdata[31]}},memdata[31:16]}:
	(lordM==`Sign_LHU && offset[1]==1'b0)?{{16{0}},memdata[15:0]}:
	(lordM==`Sign_LHU && offset[1]==1'b1)?{{16{0}},memdata[31:16]}:
	(lordM==`Sign_LW)? memdata:
	32'b0;
	assign addrload = (lordM==`Sign_LH && offset[0]!=0)||(lordM==`Sign_LHU && offset[0]!=0)||(lordM==`Sign_LW && offset!=2'b00);
endmodule
